Digital Design and Hardware Description Languages¶

RTL

Module 1 · Digital Design & HDL

Turn Boolean logic and sequential circuits into testable RTL.

Artifact: Verilog/SystemVerilog block · Measure: simulation coverage, timing, resource use

Phase 1, section 1 — combinational and sequential logic, memory technologies at a digital level, and Verilog (and related HDL practice) so you can express hardware you will later map to FPGAs and accelerators.

This module merges what were previously separate digital fundamentals and HDL tracks into one numbered section. Work through the two guides below in order (or in parallel if you already know basic logic).

1. Digital design fundamentals¶

Digital Design Fundamentals — Number systems, Boolean algebra, combinational and sequential logic, memory (SRAM, DRAM, ROM), timing intuition, and project ideas (breadboard through small RTL blocks).

2. Hardware description languages¶

Hardware Description Languages (HDLs) — Verilog syntax and semantics, modeling styles, testbenches, synthesis-oriented thinking, and small RTL projects.

Next in Phase 1¶

Computer Architecture and Hardware — ISA through memory hierarchy and real platforms, so you know what your gates and RTL will sit next to in a system.