Tag: systemverilog

All the articles with the tag "systemverilog".

• A UART-driven FPGA miner in pure PL — TIP5 on three VU35P UltraScale+, no soft processor, programmed through a Zynq 7010

  7 Aug, 2025

  A pure-PL TIP5 miner on three VU35P UltraScale+ FPGAs (Osprey E300): soft UART, AXI master, and control FSM with no processor, programmed via a Zynq 7010.

• Parallel TIP5 hashing on AMD Virtex UltraScale+ FPGAs — designing a Neptune Cash miner on AWS EC2 F2

  16 Apr, 2025

  Designing a TIP5 hash accelerator on AWS EC2 F2 Virtex UltraScale+ — the hard part was the Shell/CL PCIe interface: AppPF BARs and an AXI4-Lite register map.