Tag: vivado

All the articles with the tag "vivado".

• A UART-driven FPGA miner in pure PL — TIP5 on three VU35P UltraScale+, no soft processor, programmed through a Zynq 7010

  7 Aug, 2025

  A pure-PL TIP5 miner on three VU35P UltraScale+ FPGAs (Osprey E300): soft UART, AXI master, and control FSM with no processor, programmed via a Zynq 7010.